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No? I didn't either, but it's there, right between pins 9 and 10.

So, I was wondering why my DRC was complaining about a clearance issue, can you see it?

I'm sure that those two I²C lines aren't too long and *totally* won't get in the way of anything else I want to route on that layer, at all.

I'm really happy it's starting to actually look like a kinda finished product.

Somehow my configuration.nix ended up being 300 lines long and I'm *still* not happy with it, but it's 0300

.@SamtecInc@twitter.com has this really nifty part generator on their site.

Ouch mezzanine connectors are expensive.... maybe I should just go with standard pin headers

That looks a *little* better, still not happy with it.

Jfc that's a mess... I do not like the pinout of the QSPI flash module, *all* the traces cross each other it seems.

Leave it to Xilinx to have a 144 page document where it only talks about clocking the FPGA

As a whole the board is still pretty messy, and not everything is there yet (Still missing the osc/clock buffer, and the whole power regulation stuff, pin headers for expansion IO)

But hey, progress~

That's looking quite satisfying if I do say so myself~

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niu.moe

Welcome to your niu world ! We are a cute and loving international community O(≧▽≦)O !