Okay so not quite as successful as I would have liked, but *shrug*

Why is it always that D+/D- are swapped when adding something like a USB PHY. I just want to run the trace easily T_T

So, the "TI Confidential - NDA Restrictions" watermark in this datasheet is just a layer in the PDF that I can turn off / remove.

GG TI.

Companies keep leaking internal paths and stuff to me in datasheets, why?

Chonky connector (This might be a bit overkill)

I don't know if you can call the LED colours an easter egg or not, but oh well.

So all that's left to do is sort the power supply stuff for the 1v1, 1v8, 3v3, 5v0, and 21v0 rails, layout the decoupling caps for the FPGA, and then route everything so it's not crazy.

(Well that and document what's connected to what)

Almost done~

Wew, got the firmware building properly with Meson~

That's right, one whole USB. I don't know why they think I'd want more, one is more than enough...

No? I didn't either, but it's there, right between pins 9 and 10.

So, I was wondering why my DRC was complaining about a clearance issue, can you see it?

I'm sure that those two I²C lines aren't too long and *totally* won't get in the way of anything else I want to route on that layer, at all.

I'm really happy it's starting to actually look like a kinda finished product.

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niu.moe

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