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FPGAs are fun even when they're cursed.
Or maybe they're fun because they're cursed?

@petit
- verilog has weird semantics, esoecially when operating on bit vectors of different size
- FPGA toolchains don't really compile verilog, they do pattern matching on verilog constructs and try to find things which look kinda similar to what's available on the FPGA
- FPGA toolchains spit out lots of useless warnings, and then a ton of non-warnings, like informational messages on what they're doing. This makes it impossible to notice a warning that's actually important
- FPGA toolchains are proprietary
- it's hard to debug stuff because you don't have enough leds, and even if you did, things are happening too quickly to notice

@petit
And I didn't even mention specific fuckups of specific evaluation board manufacturers

@Wolf480pl @petit well, there is that one toolchain that isn't, but it's limited to a few Lattice FPGAs (but not the MachXO3 boards I have) and has preliminary support for some Xilinx stuff

the thing with the proprietary toolchains is they are also incredibly shitty, I remember ISE locking up or throwing graphic artefacts on the screen when I was trying to select text FFS

I hope I'll manage to return to the fpga stuff eventually and go beyond the "fade onboard LEDs with PWM" step - last time I had time for this I was trying to write an UART and failed miserably

@m0n5t3r
AFAIK ISE is best used from commandline in a VM.
But even then it can segfault randomly, and then you have to randomly permute the netlist until it stops segfaulting. Or at least that's what happened to my teacher.
@petit

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