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Hey there! () :blobheartcat:

I'm a software developer. I make video games and FOSS libraries in my spare time. I am a Linux enthusiast, and I really like old arcade games! :blobtea:

Usually I try to keep my posts light and happy on this account. Occasionally I will post a lot about projects I am working on, but I try to lock the text dumps under CWs to not hurt your timeline. :patcat:

!! OwO !!

It just seems like some basic delay constants might reflect some theoretical final fabrication outside of just "instant". However, perhaps it's confusing to debug logic containing needless delay propagations.

So, for HDLs, is it too much to define gate delays solely for simulation purposes? That's what they are there for, but most Verilog code I see doesn't seem to use delays unless a property if propagation is used in a specific module.

BitShift :bun: boosted

For context, I want to create a processor in some HDL, and then be able to clock-step the processor and change high/low pin signals from C.

Learning Verilog HDL this weekend. I want to say I'd prefer VHDL from what I've read, but Verilog has more useful FOSS tooling from what I've seen.

Is this true, or am I missing something? It seems like the big player in FOSS VHDL simulators land is GHDL.

BitShift :bun: boosted

I always find myself abandoning my Niu account for weeks at a time because I get super focused on something IRL.

I suppose that is a good thing, but then I miss all the bun posts. :bun_mood:

I want to at least log in and see the splatpocalypse unfold. But I haven't played Splatoon in such a long time I will probably do terrible.

BitShift :bun: boosted
BitShift :bun: boosted

~200 FLAC files (~6GB) took 20 seconds to convert to MP3 :)

Yay new computer!

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Welcome to your niu world ! We are a cute and loving international community O(≧▽≦)O !